Application of VHDL in EDA Simulation
JIN Fenglian
(Department of Information Engineering, Dalian Institute of L ight Industry, Dalian,116034,China)
Abstract:The Very High Speed Integrated Circuit Hardware De scription Language(VHDL)and its basic features are introduced the advantages o f VHDL in EDA are discussed, with an example, the control circuit of the traff ic signal lamp, th e methods of devising digital circuit by VHDL is introduced, and the important r ole played by VHDL in the simulative of digital circuit design is described th e waveform of time analyzer simulation is showedSimulation results verify tha t VHDL is feasible in digital circuit design and simulating, satisfactory result s are achieved, tracking the transient process sensitively
Keywords:VHDL; simulation; EDA; digital circuit
随着电子技术的发展,数字系统的设计正朝高速度、大容量、小体积的方向发展,传统的自 底而上的设计方法已难以适应形势。EDA(Electronic Design Automation)技术 的应运而生,使传统的电子系统设计发生了根本的变革。EDA技术就是依赖功能强大的计算机,在EDA工具软件平台上,对以硬件描述语言VHDL(Very High Speed Integrated Circui t Hardware Description Language)为系统逻辑描述手段自顶而下地逐层完成相应的描述 、综合、优化、仿真与验证,直至生成器件。VHDL语言是目前应用于数字系统仿真最为实 用的语言之一。